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| 74HC595 GENERAL DESCRIPTION 8-Bit Shift Registers W ith Latched 3-State Output 74HC595 is fabricated with high-speed silicon gate CMOS technology. It contains an 8-bit serial-in, serial or parallel-out shift register and an 8-bit D-type storage register with parallel 3-state outputs. The shift and storage register have independent clock inputs. Both the shift register clock (SRCK) and storage register clock (RCK) are positive-edge triggered. The shift register has a direct overriding clear input (SRCL), serial data input (SER), and serial outputs for cascading. When the output-enable (OE) input is high, the outputs are in the high-impedance state. If both clocks are connected together, the shift register always is one clock pulse ahead of the storage register. FEATURES * * * * * * * * * 8-bit serial-in, parallel-out shift register with storage Shift register has direct clear 8-bit D-type storage register with parallel 3-state outputs Two independent clocks for shift and storage register Wide operating power supply voltage 2-6V Low input current < 1A Low power consumption, Max. 80A (74HC595) Output driving capacity 6 mA at 5V Typical propagation delay 13nS LOGIC DIAGRAM Q1 15 Q2 1 Q3 2 Q4 3 Q5 4 Q6 5 Q7 6 Q8 7 13 OE 3R C3 3S 3R C3 3S 3R C3 3S 3R C3 3S 3R C3 3S 3R C3 3S 3R C3 3S 3R C3 3S 12 RCK 11 SRCK 14 SER 10 1D C1 R 2S 2R C2 R 2S 2R C2 R 2S 2R C2 R 2S 2R C2 R 2S 2R C2 R 2S 2R C2 R 2S 2R C2 R 9 Q8' SRCL 1 WS74HC595 FUNCTIONAL DESCRIPTION 1. Truth Table Inputs Function SER SRCK SRCL RCK OE X X X L X X X X X L X X X H L X Outputs Q1-Q8 are disabled. Outputs Q1-Q8 are enabled. Shift register is cleared. H X X First stage of the shift register goes low. Other stages store the data of previous stage, respectively. H H X X First stage of the shift register goes high. Other stages store the data of previous stage, respectively. X X X X Shift-register data is stored in the latch. H = High Level (steady state). L= Low Level (steady state) X = Irrelevant (don't care) = Transition from low to high level. 2. Logic Waveform SRCK SER RCK SRCL OE Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q8' Note: implies that the outputs are in 3-state mode. 2 WS74HC595 ABSOLUTE MAXIMUM RATINGS Parameter Value Unit DC supply voltage Vcc - 0.5 ~ + 7.0 V DC input clamp current Iik (Vi<0 or Vi>Vcc) 20 mA DC output clamp current Iok (Vo<0 or Vo>Vcc) 20 mA DC Current Drain per pin, any output (Iout) 35 mA DC supply Current, Vcc or GND (Icc) 70 mA Storage Temperature( TSTG) -65 ~ +150 Lead Temperature(TL) (Soldering, 10seconds) 260 Note: 1. Absolute maximum ratings are those values beyond which the safety of the device cannot be guaranteed. RECOMMENDED OPERATING CONDITONS Parameter Power Supply Voltage (Vcc) VCC=2.0V Min. Normal Max. Unit 2 VCC=4.5V 5 6 V VIH High-level input voltage VCC=6.0V 1.5 3.15 4.2 V VCC=2.0V VIL Low-level Input Voltage VCC=4.5V VCC=6.0V 0.5 1.35 1.8 V VI Input Voltage VO Output Voltage Operating Temperature (TA) 74HC595 0 0 -40 Vcc Vcc 85 V V Input Rise/Fall Times (tr, tf) VCC=2.0V VCC=4.5V VCC=6.0V 1000 500 400 ns Note: 2. All unused inputs of the device must be held at Vcc or GND to ensure proper device operation. 3. If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and Vcc = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. 3 WS74HC595 DC ELECTRICAL CHARACTERISTICS (Apply across temperature range unless otherwise specified) TA = 25 54HC595 TYP MAX MIN 1.998 1.9 4.499 4.4 5.999 5.9 4.3 3.84 5.8 5.34 0.002 0.1 0.001 0.1 0.001 0.1 0.17 0.26 0.15 0.26 100 0.1 0.01 0.5 8 3 10 74HC595 MAX PARAMETER TEST CONDITIONS Vcc MIN 1.9 4.4 5.9 3.98 5.48 UNIT VOH VOL II 2V IOH = -20uA 4.5V VI= VIH or VIL 6V IOH = -6 mA 4.5V IOH = -7.8mA 6 V 2V IOL =20uA 4.5V VI= VIH or VIL 6V IOL = 6mA 4.5V IOL =7.8mA 6 V VI = Vcc or 0 6V V IOZ Icc Ci VO = Vcc or 0, Q1-Q8 VI = Vcc or 0 IO = 0 6V 6V 2V ~ 6V 0.1 0.1 0.1 V 0.33 0.33 1000 nA 5 uA 80 uA 10 pF TIMING REQUREMENTS OVER RECOMMENED OPERATING FREE-AIR TEMPERATURE RANGE (unless otherwise noted) Parameter Symbol Unit Guaranteed Limit Test Condition Clock frequency fclock MHz Pulse duration tw ns Setup time tsu ns Hold time, th ns TA=25 6 31 36 80 16 14 80 16 14 100 20 17 75 15 13 50 10 9 50 10 9 0 -40~+85 5 Vcc=2.0V 25 Vcc=4.5V 29 Vcc=6.0V 100 Vcc=2.0V SRCK or LCK high or low 20 Vcc=4.5V 17 Vcc=6.0V 100 Vcc=2.0V SRCL low 20 Vcc=4.5V 17 Vcc=6.0V 125 Vcc=2.0V 25 Vcc=4.5V SER before SRCK 21 Vcc=6.0V 94 Vcc=2.0V 19 Vcc=4.5V SRCK before LCK (Note 4) 16 Vcc=6.0V 65 Vcc=2.0V 13 Vcc=4.5V SRCL low before RCK 11 Vcc=6.0V 60 Vcc=2.0V SRCL high(inactive) 12 Vcc=4.5V 11 before SRCK Vcc=6.0V 0 Vcc=2~6V SER after SRCK Note: . 4. This setup time allows the latch to receive stable data from the shift register. The clock can be connected together, in this case the shift register is one clock pulse ahead of the latch. 4 WS74HC595 AC ELECTRICAL CHARACTERISTICS (unless otherwise noted) Parameter Symbol From To Unit (Input) (Output) MHz Vcc Maximum clock frequency fmax Ta = 25 Min Typ Max 2V 6 26 4.5V 31 38 6V 36 42 2V 50 160 4.5V 17 32 74HC595 Parameter Min 5 25 29 Max CL=50pF SRCK Q8' ns 200 40 Maximum Propagation Delay (Clock to Q) tpd LCK Q1-Q8 ns 6V 2V 4.5V 6V 2V 14 50 17 27 150 30 14 60 26 200 34 187 37 32 250 CL=50pF LCK Maximum Propagation Delay (SRCL to Q8' Q1-Q8 ns tPHL SRCL QH' 4.5V 6V 2V 22 40 19 51 34 175 50 43 219 CL=150pF ns 4.5V 6V 18 35 15 40 15 13 30 44 37 CL=50pF Maximum Propagation Delay (OE to Q) 2V 4.5V 6V ten OE Q1-Q8 ns 2V 4.5V 6V 2V tdis OE Q1-Q8 ns 4.5V 6V 2V 4.5V 6V 2V Q1-Q8 Maximum Output Rising and Falling Time tt Q8' ns 4.5V 6V 2V 4.5V Q1-Q8 Power Dissipation Capacitance 6V CPD pF 150 30 26 70 200 23 40 19 34 42 200 23 40 20 34 28 60 8 12 6 10 28 75 8 15 6 13 45 210 17 42 13 36 400 187 37 32 CL=50pF 250 50 43 CL=150pF 250 50 43 75 15 13 95 19 16 265 53 CL=50pF CL=50pF CL=150pF 45 - - PARAMETER MEASUREMENT INFORMATION Vcc Test Point From Output Under Test PARAMETER RL CL S1 S2 S1 RL ten S2 CL tdis tPZH tPZL tPHZ tPLZ 1 k 50 pF 150 pF 1k 50 pF or Open Closed Closed Open Closed Open Closed Open Open tpd or tt - 50 pF 150 pF or Open 5 WS74HC595 AC SWITCHING WAVEFORM AND AC TEST CIRCUIT Voltage Waveforms 1. Propagation Delay and Output Transition Times Input Vcc 50% tPLH 50% 0V tPHL In-Phase Output 50% 10% tPHL 90% 90% tr Out-of-Phase Output 50% 10% tf VOH 50% 10% VOL tf tPLH VOH 90% 50% 10% VOL 90% tr Voltage waveforms 2. Enable And Disable Times For 3-State Outputs Output Control (Low-Level Enabling) Output Waveform1 50% tPZL Vcc 50% 50% tPLZ Vcc 0V Vcc VOL VOH 0 V 10% 90% tPHZ tPZH Output Waveform 2 50% Voltage waveforms 3. Setup And Hold and Input Rise And Fall Times Reference Input 50% Vcc 0V tsu th 90% Vcc 50% 10% tf Data Input 50% 10% 90% tr 0V 6 WS74HC595 Voltage waveforms 4. Pulse Durations High-Level Pulse 50% tw Vcc 50% 0V Vcc Low-Level Pulse 50% 50% 0V Note: 5. CL includes probe and test-fixture capacitance. 6. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 , tr = 6 ns, tf = 6 ns. 7. For clock inputs, fmax is measured when the input duty cycle is 50%. 8. The outputs are measured one at a time, with one input transition per measurement. 9. tPLZ and tPHZ are the same as tdis. 10. tPZL and tPZH are the same as ten. 11. tPLH and tPHL are the same as tpd. PIN DESCRIPTION PIN NO. SYMBOL DESCRIPTION 15, 1, 2, 3, 4, 5, 6, 7 9 10 11, 12 13 14 8 16 Q1 - Q8 Q8' SRCL SRCK, RCK OE SER GND VCC Parallel data outputs Serial data output Shift register reset input (active low) Shift and storage register clock inputs (triggered at positive edge) Output enable input (active low) Serial data input Ground (0V) Positive power supply 11 SRCK Q2 Q3 Q4 Q5 Q6 Q7 1 16 Vcc Q1 SER OE RCK 12 RCK 9 Q8' 15 Q1 Q2 1 2 Q3 3 Q4 4 Q5 5 Q6 6 Q7 Q8 7 OE 14 SER SRCK Q8 SRCL 8 9 SRCL GND Q8' 10 13 Pin Configuration Logic Symbol 7 WS74HC595 PAD DIAGRAM SRCK Q8' The Coordinate of Each Pad GND Q8 SRCL RCK OE Q7 (-615.1, -748.2) Q6 Q7 Q8 (479.8, 185.0) (479.8, 379.6) (479.8, 635.4) SER (-398.1, -748.2) Q1 (-243.3, -762.4) 74HC595 Die Size = 57 mil X 74 mil Pad Size = 90 um X 90 um Q6 VCC (118.3, -789.2) Q2 Q5 GND (105.8, 683.3) Q8' (-199.4, 683.3) SRCL (-359.7, 673.2) SRCK (-581.0, 689.2) RCK (-600.9, 534.4) (479.8, -714.6) (479.8, -520.6) (479.8, -264.8) (479.8, -70.2) Q3 Q4 Q4 Q5 Q3 Note: OE SER Substrate should be connected to Vcc or left it open. Q1 Q2 VCC 8 |
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